Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods, structures, and systems for preparing semiconductor devices comprising fins with improved nanosheet spacers.
Description of the Related Art
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Generally, a set of processing steps is performed on a group of semiconductor wafers, sometimes referred to as a lot, using semiconductor-manufacturing tools, such as exposure tool or a stepper. As an example, an etch process may be performed on the semiconductor wafers to shape objects on the semiconductor wafer, such as polysilicon lines, each of which may function as a gate electrode for a transistor. As another example, a plurality of metal lines, e.g., aluminum or copper, may be formed that serve as conductive lines that connect one conductive region on the semiconductor wafer to another. In this manner, integrated circuit chips may be fabricated.
Fin field-effect transistors (FinFET) devices have been developed to replace conventional planar bulk MOSFETs in advanced CMOS technology by improving electrostatic control of the channel. Extending the concept of the finFET to further improve electrostatics involves developing structures where the gate wraps around the complete channel to form “gate-all-around” (GAA) devices. In GAA devices, the surrounded channels may comprise wires with rectangular or circular cross section, or sheets with a rectangular cross-section, which may be termed “nanowire devices” or “nanosheet devices”. To improve current density per footprint, these sheets or wires can be formed in a vertically stacked fashion, where multiple channels are formed one atop the other. Such nanowire/nanosheet devices therefore comprise multiple stacked semiconductor channel layers separated by sacrificial suspension material that is removed when performing a replacement metal gate (RMG) process in order to release the channel layers, which requires the devices to complete the majority of the FEOL flow similarly to a FinFET with sacrificial suspension layers remaining.
Nanosheet devices generally require, during intermediate processing stages, spacer formation. If the spacer is misformed, subsequent epitaxial growth of source/drain elements from semiconductor sheets may at least in part nucleate from the sacrificial suspension material instead of the semiconductor sheets. Epitaxially-grown source/drain elements resulting from nucleation from sacrificial suspension material may therefore be unintentionally etched away during the channel release process, cause undesirable shorting or the introduction of unintended leakage paths in the final device.
The present disclosure may address and/or at least reduce one or more of the problems identified above regarding the prior art and/or provide one or more of the desirable features listed above.